Method and an apparatus for a hard-coded bit value changeable in any layer of metal

ABSTRACT

A method is disclosed to make a hard-coded bit in an integrated circuit on a semiconductor chip changeable in any one and only one metal layer of the semiconductor chip. In one embodiment, the method further comprising fabricating a cell on each metal layer of the semiconductor chip and a logic circuitry on the semiconductor chip. The cells are coupled to the inputs of the logic circuitry. The output of the logic circuitry changes in response to a change in any single cell to cause the hard-coded bit to change.

FIELD OF INVENTION

[0001] The present disclosure relates to the fabrication ofsemiconductor chips, and more particularly, to changing the value of ahard-coded bit on a semiconductor chip during fabrication.

BACKGROUND

[0002] Integrated electronic circuits fabricated on a semiconductor chiptypically include a number of hard-coded bits for various purposes. Forexample, a revision identifier on a semiconductor chip includes a numberof hard-coded bits to indicate which stepping of the mask is used tofabricate the chip. A new stepping of the mask is created every time thelayout of the semiconductor chip is changed, and a distinct revisionidentifier, also known as a stepping ID, is assigned to each stepping.Typical examples of revision identifier include “A0,” “A1,” “B1,” or“B2,” etc.

[0003] The layout of an integrated circuit is changed when a functionalchange is made in the integrated circuit. Changing the layout requirescreating a new stepping. Consequently, the revision identifier has to bechanged as well when a functional change is made in the integratedcircuit.

[0004] Currently, there are two methods to implement a hard-coded bitvalue in a semiconductor chip. The first method implements thehard-coded bit value as a part of the register transistor level (“RTL”)code. Since the hard-coded bit value is generated by the RTL code, thebit is not associated with one and only one metal layer. Therefore,multiple metal layers are modified to change the bit.

[0005] The second method to implement a hard-coded bit value in asemiconductor chip is to fabricate a custom-built metal structure on thesemiconductor chip to couple Vss or Vcc to the hard-coded bit. FIG. 1Ashows a metal structure 130 on a semiconductor chip (not shown) with ahard-coded bit 110 at one end of the metal structure 130. The hard-codedbit 110 is coupled to Vss 140 via a connection 120 in between the metalstructure 130 and Vss 140, and therefore, the hard-coded bit 110 is setto logic 0. Changing the metal layers of the semiconductor chip changesthe metal structure to cause a change in the hard-coded bit. However,once a connection is created in a metal layer, subsequent changes of themetal structure requires cutting off the connection regardless ofwhether the functional change is in the same metal layer as theconnection is in. In other words, two or more metal layers have to bechanged in order to change the hard-coded bit.

[0006] Suppose the functional change in the new stepping requireschanging only the metal layer 160. The new stepping also needs a newrevision identifier. Therefore, the hard-coded bit 110 on the metalstructure 130 has to be changed. Referring to FIG. 1B, the metal layer150 is changed to remove the connection 120 in order to cut off themetal structure 130 from Vss 140. In addition, a connection 170 isfabricated in metal layer 160 to couple the metal structure 130 to theVcc 180 to change the hard-coded bit from logic 0 to logic 1. It isnecessary to remove the connection 120 in the metal layer 150 to allow achange in the hard-coded bit 110 on the metal structure 130 regardlessof which metal layer is changed to implement the functional change inthe new stepping. As a result, two metal layers are changed even thoughthe functional change requires changing only one metal layer.

[0007] As explained above, the change of the revision identifierassociated with a new stepping is not necessarily in the same metallayer as the functional change in the integrated circuit using thecurrent methods. Frequently, changing the revision identifier requireschanging more metal layers than the functional change requires. Changinga metal layer typically costs $10,000. As a result, the more metallayers are changed in a stepping, the more expensive the stepping is.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present invention will be understood morefully from the detailed description that follows and from theaccompanying drawings, which however, should not be taken to limit theappended claims to the specific embodiments shown, but are forexplanation and understanding only.

[0009]FIG. 1A shows a hard-coded bit set at logic 0 implemented with ametal structure.

[0010]FIG. 1B shows a hard-coded bit set at logic 1 implemented with ametal structure.

[0011]FIG. 2A shows one embodiment of a hard-coded bit implemented withfour tieoff cells and a logic circuitry.

[0012]FIG. 2B shows another embodiment of a hard-coded bit implementedwith six tieoff cells and a logic circuitry.

[0013]FIG. 2C shows an embodiment of hard-wired cells coupled to metallayers.

[0014]FIG. 2D shows an embodiment of a revision identifier.

[0015]FIG. 2E shows an embodiment of a feature selection bit.

[0016]FIG. 3A shows the cross-section of an embodiment of a tieoff cellset at logic 1.

[0017]FIG. 3B shows the cross-section of an embodiment of a tieoff cellset at logic 0.

[0018]FIG. 4A shows the top view of an embodiment of a tieoff cell setat logic 1.

[0019]FIG. 4B shows the top view of an embodiment of a tieoff cell setat logic 0.

[0020]FIG. 5 shows an exemplary embodiment of a computer system.

DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are setforth. However, it is understood that embodiments of the invention maybe practiced without these specific details. In other instances,well-known circuits, structures, and techniques have not been shown indetail in order not to obscure the understanding of this description.

[0022]FIG. 2A shows an embodiment that implements a hard-coded bit 210.The hard-coded bit 210 is generated by a logic circuitry 220 fabricatedon a semiconductor chip (not shown). The semiconductor chip has a numberof tieoff cells 231-234. In addition to tieoff cells, other types ofcells or structures that can be set to either logic 1 or logic 0 can beused. At least one tieoff cell is fabricated on each metal layer of thesemiconductor chip. For example, the embodiment shown in FIG. 2A hasfour metal layers, and the tieoff cell 231 is from the first metallayer, the tieoff cell 232 is from the second metal layer, and so on.The tieoff cells 231-234 are coupled to the inputs of the logiccircuitry 220.

[0023] In an alternate embodiment, two cells are provided for each metallayer. For example, referring to FIG. 2C, the cells M1L0 281 and M1L1282 are provided for the metal layer M1. Cell 281 is hard-wired to logic0 and cell 282 is hard-wired to logic 1. Cell 281 is coupled to themetal layer M1 287 via the connection 285 and cell 282 is isolated fromthe metal layer 287. The metal layer 287 is coupled to one of the inputsof the logic circuitry (not shown). Therefore, an input of logic 0 isprovided via the metal layer 287 to the logic circuitry. Similarly, cell283 is hard-wired to logic 0 and cell 284 is hard-wired to logic 1. Cell284 is coupled to the metal layer M2 288 via the connection 286. Themetal layer 288 is coupled to the input of the logic circuitry (notshown), providing an input of logic 1 to the logic circuitry.

[0024] Referring to FIG. 2A, the output of the logic circuitry 220 isthe hard-coded bit 210. In another embodiment, the output of the logiccircuitry 220 is coupled to the hard-coded bit via additional circuitcomponents to cause the hard-coded bit to change in response to theoutput of the logic circuitry 220.

[0025] The logic circuitry 220 is configured such that changing anysingle tieoff cell of the tieoff cells 231-234 changes the output of thelogic circuitry 220 regardless of the initial values of the tieoff cells231-234. Changing one tieoff cell requires changing only one metallayer, which is the metal layer the tieoff cell is on. Therefore, thehard-coded bit is changeable by changing any single metal layer.Moreover, the hard-coded bit can be changed again later in anotherstepping without undoing the change made to a tieoff cell in an earlierstepping. In one embodiment, the functional change in a steppingrequires changing more than one metal layer, say X metal layers. Tochange the hard-coded bit in the stepping, any one tieoff cell chosenfrom the X tieoff cells on the X metal layers can be changed.

[0026] In one embodiment, the logic circuitry 220 includes an exclusiveOR (“XOR”) circuit. The output of the XOR circuit changes when anysingle input signal changes. Referring to FIG. 2A, the embodiment of thelogic circuitry 220 shown includes an XOR circuitry made up of three2-input XOR gates 221-223. The tieoff cell 231 and the tieoff cell 232are input to the XOR gate 221, and the tieoff cell 233 and the tieoffcell 234 are input to the XOR gate 222. The outputs of both XOR gates221 and 222 are input to the XOR gate 223. The output of the XOR gate223 is the output of the logic circuitry 220. The output of the XOR gate223 changes in response to a change in any one of the tieoff cells231-234. Suppose all four tieoff cells 231-234 are at logic 0 initially.Then the output signals of both XOR gates 221 and 222 are at logic 0,which are input to the XOR gate 223. Since both input signals to the XORgate 223 are at logic 0, the XOR gate 223 generates an output at logic0. Since the hard-coded bit 210 is the output of the XOR gate 223 in theembodiment shown in FIG. 2A, the hard-coded bit 210 is at logic 0.

[0027] To change the hard-coded bit 210 to logic 1, any one of thetieoff cells 231-234 can be changed. For example, suppose the tieoffcell 231 is changed from logic 0 to logic 1, while the other tieoffcells 232-234 remain at logic 0. The output of the XOR gate 221 istherefore changed from logic 0 to logic 1. Since the tieoff cells 233and 234 remain at logic 0, the output of the XOR gate 222 remains atlogic 0. The outputs of the XOR gate 221 and the XOR gate 222 are inputto the XOR gate 223, that is, a logic 0 and a logic 1 are input to theXOR gate 223. The input of a logic 0 and a logic 1 causes the output ofthe XOR gate 223 to change from logic 0 to logic 1. The hard-coded bit210 is the output of the XOR gate 223 in the embodiment shown in FIG.2A, and therefore, the hard-coded bit 210 is changed from logic 0 tologic 1. One should appreciate that any one of the tieoff cells 231-234can be changed to change the output of the XOR gate 223 regardless ofthe initial values of the tieoff cells. Moreover, when the output of theXOR gate 223 has to be changed again, it is not necessary to undo theearlier change made to the tieoff cell 231 because the output of the XORgate 223 changes as long as any one of the tieoff cells 231-234 ischanged regardless of the initial state of the tieoff cells 231-234.

[0028] To implement a semiconductor chip with the hard-coded bit usingadditional metal layers, additional logic gates are added to the logiccircuitry 220. FIG. 2B shows one embodiment of a semiconductor chip witha hard-coded bit and six metal layers. Each of the metal layers (notshown) has a tieoff cell. For example, the tieoff cell 261 is on thefirst metal layer, the tieoff cell 262 is on the second metal layer, andso on. The tieoff cells 261 and 262 are input to the XOR gate 271. Thetieoff cells 263 and 264 are input to the XOR gate 272. The tieoff cells265 and 266 are input to the XOR gate 273. The outputs of the XOR gates271 and 272 are input to the XOR gate 274. The output of the XOR gate274 and the output of the XOR gate 273 are input to the XOR gate 275. Inone embodiment, the output 280 of the XOR gate 275 is the hard-coded bit210. In another embodiment, the output 280 of the XOR gate 275 iscoupled to the hard-coded bit to cause the hard-coded bit to change inresponse to the output of the XOR gate 275.

[0029] Changing any single tieoff cell of the tieoff cells 261-266 willchange the output of the XOR gate 275, causing a change in thehard-coded bit 280. For example, suppose the tieoff cells 261-266 areall at logic 0 initially. Then the outputs of the XOR gates 271-275 areall at logic 0. When only the tieoff cell 261 is changed from logic 0 tologic 1, the output of the XOR gate 271 changes from logic 0 to logic 1.The output of the XOR gate 271 is input to the XOR gate 274, causing theoutput of the XOR gate 274 to change from logic 0 to logic 1. The outputof the XOR gate 274 is input to the XOR gate 275, causing the output ofthe XOR gate 275 to change from logic 0 to logic 1. Since the output 280of the XOR gate 275 is the hard-coded bit 280 in the embodiment shown inFIG. 2B, the hard-coded bit 280 is changed from logic 0 to logic 1.

[0030] One should appreciate that the above embodiments of the logiccircuitry 220 are provided for the purpose of illustration only. Theimplementation of the logic circuitry 220 is not limited to XOR gates orXOR logic circuitries. Other combinations of logic circuitries are usedin other embodiments to allow the hard-coded bit to be changed bymodifying the tieoff cell on any single metal layer.

[0031] In one embodiment, the hard-coded bit is part of a revisionidentifier 2200 of the semiconductor chip. FIG. 2D shows an embodimentof an eight-bit revision identifier. Referring to FIG. 2D, the revisionidentifier 2200 has 8 bits, Rev_ID7-Rev_ID0. Other embodiments of therevision identifier have different number of bits, such as, 4, 16, etc.The semiconductor chip has 4 metal layers (not shown), each metal layerhaving 8 tieoff cells. For example, the first metal layer has the tieoffcells 2001, 2011, 2021, 2031, 2041, 2051, 2061, and 2071. There are atotal of 32 tieoff cells 2001-2004, 2011-2014, 2021-2024, 2031-2034,2041-2044, 2051-2054, 2061-2064, and 2071-2074. Four tieoff cells, onefrom each metal layer, are input to an XOR gate. There are eight XORgates on the semiconductor chip. Each XOR gate is coupled to a bit ofthe revision identifier 2200 to cause the bit to change in response to achange in one of the input tieoff cells. For example, the eighth bit ofthe revision identifier 2200, Rev_ID7 2207 is coupled to the output ofthe XOR gate 2307 and the tieoff cells 2071-2074 are input to the XORgate 2307. A change in any one of the tieoff cells 2071-2074 causes theoutput of the XOR gate 2307 to change, and consequently, causes Rev_ID72207 to change.

[0032] As explained above, the revision identifier changes with everystepping. In one embodiment, a new stepping is required due to afunctional change implemented as a change on only one metal layer of thesemiconductor chip. Since the hard-coded bits of the revision identifiercan be changed in any metal layer, it is advantageous to change thehard-coded bits of the revision identifier on the same metal layer asthe functional change to reduce the number of metal layers changed.Reducing the number of metal layers changed reduces the cost of thestepping.

[0033] In another embodiment, the hard-coded bit is a feature selectionbit in an integrated circuit. The integrated circuit has a number ofoperating modes, which are selectable during the fabrication of theintegrated circuit using the feature selection bit. In one embodiment,the feature selection bit can be set at logic 1 or logic 0 to enable ordisable one or more of the operating modes. To change the featureselection bit in a stepping, a tieoff cell on any single metal layer isswitched to the opposite logic value.

[0034]FIG. 2E shows one embodiment of a feature selection bit on asemiconductor chip. There are four tieoff cells 2081-2084, each on adistinct metal layer of the semiconductor chip. The tieoff cells2081-2084 are input to the XOR gate 2400, which outputs the featureselection bit 2450. The feature selection bit 2450 opens or closes theswitch 2500 to enable or to disable a feature of the semiconductor chip.

[0035] Referring to FIG. 2E, an embodiment of the switch 2500 includes ap-type Metal Oxide Semiconductor transistor (“pMOS”) 2510, an n-typeMetal Oxide Semiconductor transistor (“nMOS”) 2520, and an inverter2530. When the feature selection bit 2450 is at a high voltage, the NMOS2520 is activated. The inverter 2530 converts the high voltage of thefeature selection bit 2450 to a low voltage and applies the low voltageat the gate of the pMOS 2510 to activate the pMOS 2510. Therefore, thefeature selection bit 2450 closes the switch 2500. When the featureselection bit 2450 is at a low voltage, it deactivates the nMOS 2520 andthe pMOS 2510 to open the switch 2500. One should appreciate that theabove embodiments are described for the purpose of illustration only,and they do not limit the applications of the hard-coded bits on asemiconductor chip. The hard-coded bits changeable in any metal layercan be used for purposes beyond the above descriptions.

[0036]FIG. 3A shows a cross-sectional view of an embodiment of a tieoffcell 300 on a metal layer 310. The tieoff cell 300 has an output pin320. There are two via stacks 330 and 340 in the tieoff cell 300. Thevia stack 330 is coupled to Vss 335. The via stack 340 is coupled to Vcc345. Coupling the output pin 320 to the via stack 330 couples the outputpin 320 to Vss 335. Coupling the output pin 320 to Vss 335 sets thetieoff cell 300 at logic 0. On the contrary, coupling the output pin 320to the via stack 340 couples the output pin 320 to Vcc 345. Coupling theoutput pin 320 to Vcc 345 sets the tieoff cell 300 at logic 1. In FIG.3A, the output pin 320 is coupled to the via stack 340 with a connector350. The via stack 340 further couples the output pin 320 to Vcc 345,setting the output pin 320 at logic 1.

[0037]FIG. 3B shows the cross-section of an embodiment of the tieoffcell 300 set at logic 0. The connector 350 has been removed to isolatethe output pin 320 from the via stack 340. Therefore, the output pin 320is not coupled to Vcc 345 in FIG. 3B. A connector 360 is added betweenthe output pin 320 and the via stack 330 to couple the output pin 320 toVss 335. When the output pin 320 is coupled to Vss 335, the output pin320 is set at logic 0. In one embodiment, the metal layer 310 ismodified to remove the connector 350 and to add the connector 360 tocouple the output pin 320 to Vss 335 in order to change the tieoff cell300 from logic 1 to logic 0. To change the tieoff cell 300 from logic 0to logic 1, the metal layer 310 is changed to remove the connector 360and to add the connector 350 to couple the output pin 320 to Vcc 345.

[0038]FIG. 4A shows the top view of an embodiment of a theoff cell 400at logic 1. The tieoff cell 400 has an output pin 420 and two via stacks430 and 440. The via stack 430 is connected to Vss and the via stack 440is connected to Vcc. The output pin 420 is coupled to the via stack 440by the connector 450, and therefore, is coupled to Vcc. The output pin420 is isolated from the via stack 430 so that the output pin 420 isisolated from Vss. Coupling the output pin 420 to Vcc sets the tieoffcell at logic 1.

[0039]FIG. 4B shows the top view of an embodiment of the tieoff cell 400at logic 0. The output pin 420 is coupled to the via stack 430 by theconnector 460, which is coupled to Vss. The output pin 420 is isolatedfrom the via stack 440 so that the output pin 420 is isolated from Vcc.Coupling the output pin 420 to Vss sets the tieoff cell at logic 0.

[0040]FIG. 5 is a block diagram of an exemplary computer system. Thesystem 500 includes central processing unit (“CPU”) 501, memorycontroller hub (“MCH”) 502, input/output controller hub (“ICH”) 503,flash memory device to store the Basic Input Output System (“FlashBIOS”) 504, memory 505, graphics chip 506, and a number of peripheralcomponents 510. CPU 501, memory 505, graphics chip 506, and ICH 503 arecoupled to MCH 502. Data transmitted between CPU 501, memory device 505,graphics chip 506, and ICH 503 is routed through MCH 502. Peripheralcomponents 510 and flash BIOS 504 are coupled to ICH 503. Peripheralcomponents 510 and flash BIOS 504 communicate with CPU 501, graphicschip 506, and memory 505 through ICH 503 and MCH 502. Note that any orall of the components of system 500 and associated hardware may be usedin various embodiments of the present invention. However, it should beappreciated that other configurations of the computer system may includesome or all of the devices.

[0041] ICH 503 is fabricated on a semiconductor chip. The semiconductorchip has a number of metal layers. ICH 503 includes a hard-coded bit 509changeable in any single metal layer of the semiconductor chip. Thesemiconductor chip has a number of tieoff cells. There is at least onetieoff cell fabricated on each metal layer of the semiconductor chip.The tieoff cells are input to a logic circuitry. The logic circuitry isconfigured such that changing any single tieoff cell changes the outputof the logic circuitry. In one embodiment, the output of the logiccircuitry is the hard-coded bit. In another embodiment, the output ofthe logic circuitry is coupled to the hard-coded bit to cause thehard-coded bit to change in response to the output of the logiccircuitry.

[0042] To change a tieoff cell, only one metal layer has to be changed.Making the hard-coded bit to be changeable by changing any one tieoffcell allows the hard-coded bit to be changeable in any single metallayer. Moreover, the hard-coded bit can be changed again later inanother stepping without undoing the change made to a tieoff cell in anearlier stepping. If the functional change in a stepping requireschanging more than one metal layer, then a tieoff cell chosen from anyone of those metal layers can be changed to change the hard-coded bit.

[0043] The foregoing discussion merely describes some exemplaryembodiments of the present invention. One skilled in the art willreadily recognize from such discussion, the accompanying drawings andthe claims that various modifications can be made without departing fromthe spirit and scope of the appended claims. The description is thus tobe regarded as illustrative instead of limiting.

What is claimed is:
 1. A method comprising: fabricating a hard-coded bitin an integrated circuit; and changing any single metal layer of aplurality of metal layers in the integrated circuit to change thehard-coded bit value.
 2. The method of claim 1, wherein fabricating thehard-coded bit comprises: fabricating a plurality of cells, one cell oneach of the plurality of metal layers; fabricating logic circuitry inthe integrated circuit; and coupling the plurality of cells to inputs ofthe logic circuitry to generate the hard-coded bit.
 3. The method ofclaim 2, wherein changing the single metal layer to change thehard-coded bit value comprises changing a cell on the single metal layerfrom a first logic value to a second logic value.
 4. The method of claim3, wherein each of the plurality of cells includes an output pin.
 5. Themethod of claim 4, wherein changing the cell from the first logic valueto the second logic value includes: decoupling an output pin of the cellon the single metal layer from a first voltage supply; and coupling theoutput pin of the cell to a second voltage supply.
 6. The method ofclaim 2, wherein the logic circuitry comprises an exclusive OR (“XOR”)circuit.
 7. The method of claim 1, wherein the hard-coded bit is part ofa revision identifier of the integrated circuit.
 8. The method of claim1, wherein the hard-coded bit is a feature selection bit of theintegrated circuit.
 9. An integrated circuit comprising: a plurality ofmetal layers; and a hard-coded bit coupled to the plurality of metallayers, wherein the hard-coded bit value is changeable duringfabrication in any single metal layer of the plurality of metal layers.10. The integrated circuit of claim 9, further comprising a plurality ofcells, wherein there is at least one cell on each of the plurality ofmetal layers.
 11. The integrated circuit of claim 10, further comprisinga logic circuitry having a plurality of input terminals and an outputterminal, each of the plurality of input terminals coupled to each ofthe plurality of cells and the output terminal coupled to the hard-codedbit.
 12. The integrated circuit of claim 11, wherein changing any singlecell of the plurality of cells from a first logic value to a secondlogic value during fabrication causes a change in the hard-coded bitvalue.
 13. The integrated circuit of claim 12, wherein each of theplurality of cells includes an output pin.
 14. The integrated circuit ofclaim 13, wherein the output pin of each of the plurality of cells canbe decoupled from a first voltage supply and coupled to a second voltagesupply to change the value of the cell from the first logic value to thesecond logic value.
 15. The integrated circuit of claim 11, wherein thelogic circuitry comprises an exclusive OR (“XOR”) circuit.
 16. Theintegrated circuit of claim 9, wherein the hard-coded bit is part of arevision identifier.
 17. The integrated circuit of claim 9, wherein thehard-coded bit is a feature selection bit.
 18. A system comprising: agraphics chip; and an input/output controller hub, the input/outputcontroller hub including an integrated circuit, wherein the integratedcircuit comprises a plurality of metal layers; and a hard-coded bitcoupled to the plurality of metal layers, wherein the hard-coded bitvalue is changeable during fabrication in any single metal layer of theplurality of metal layers.
 19. The system of claim 18, wherein theintegrated circuit further comprises a plurality of cells, wherein thereis at least one cell on each of the plurality of metal layers.
 20. Thesystem of claim 19, wherein the integrated circuit further comprises alogic circuitry having a plurality of input terminals and an outputterminal, each of the plurality of input terminals coupled to each ofthe plurality of cells and the output coupled to the hard-coded bit. 21.The system of claim 20, wherein changing any single cell of theplurality of cells from a first logic value to a second logic valueduring fabrication causes a change in the hard-coded bit value.
 22. Thesystem of claim 21, wherein each of the plurality of cells includes anoutput pin.
 23. The system of claim 22, wherein the output pin of eachof the plurality of cells can be decoupled from a first voltage supplyand coupled to a second voltage supply to change the value of the cellfrom the first logic value to the second logic value.
 24. The system ofclaim 20, wherein the logic circuitry comprises an exclusive OR (“XOR”)circuit.
 25. The system of claim 18, wherein the hard-coded bit is partof a revision identifier.
 26. The system of claim 18, wherein thehard-coded bit is a feature selection bit.